1. Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly to two-sided wafer processing, either followed by re-slicing the wafer or detaching two previously attached wafers after the two-sided wafer processing. or including one of two subsystems of the same IC on each side of one chip.
2. Discussion of the Related Art
As the electronics industry has progressed, IC's have become more versatile and more complex. Fortunately, advances in reducing the size of IC's have paralleled progress in IC development. The advent and continued successes of photoelectron lithography, e.g., have enabled chipmakers to shrink their products tremendously by shrinking circuit element sizes. However, there is an ongoing need for new cost effective techniques for reducing the size of IC's.
Processing of a semiconductor substrate 2 on one side to form circuit elements is a well established art. FIG. 1A shows a conventional substrate 2, which may be a semiconductor or an insulator, but for most integrated circuit applications is silicon. Only one side, e.g., the topside 4 of the substrate 2, is polished for conventional one-sided processing purposes to remove coarseness and irregularities causing the topside 4 to become substantially planar.
To process the topside 4 only of a semiconductor substrate 2 after polishing, the substrate 2 is first loaded into unilateral processing equipment. The wafer may be supported anywhere on the underside 6 as no processing is to take place there. The processing is focused at one planar surface facing in only one direction at a time. After processing is performed on the topside 4, the substrate 2 is unloaded. The underside 6 of the substrate is not aligned nor processed and is often in full contact with a support during loading, processing, unloading and/or storing. In contrast, dual-side processing involves consideration of the underside 6 for loading, alignment, processing, unloading and storing.
It is known in the art to polish and process transistors and discrete devices on both the topside 4 and the underside 6 of a wafer, thereby dual-side processing the wafer. A known technique for alignment and preparation of a wafer for dual-side exposure involves mutually aligning two exposure masks and aligning the wafer in between. In U.S. Pat. No. 3,939,579 to Schmidt, mutual parallel and rotational alignment of two exposure masks is achieved by bringing first and second exposure masks in plane parallel contact, and then moving them apart in a direction perpendicular to their planes while maintaining the plane parallel alignment.
The process utilizes a pair of coupled rotational compound slide tables each having a mask support for supporting one of the two masks. The wafer is placed in air cushion free contact with the first mask and then separated by a fixed distance and aligned relative to the first mask. The second mask is moved into position a fixed distance from the wafer, and the wafer is dual-side exposed to, e.g., UV radiation.
Another technique is disclosed in U.S. Pat. No. 5,530,552 to Mermagen and Geil. In that disclosure, a flat edge of a wafer is aligned with a first and second masks in sequence utilizing a rotational alignment guide. Each mask has two windows aligned symmetrically about a vertical center line and each is aligned with an edge of the wafer. The wafer is once again dual-side exposed after alignment is completed.
Substantially congruent dual-side processing of a substrate to produce a bi-directional solid state device, or a switch, is disclosed in U.S. Pat. No. 3,928,093 to van Tangerloo et al. In that patent, each side of a silicon wafer has an oxide layer and is photoengraved and boron diffused to form P.sup.+ -type bases. Then, N.sup.+ -type emitter regions are formed on each side by photoengraving followed by phosphorus deposition and diffusion. The switching device is completed by attaching electrical contacts to the base and emitter regions after passivation and photoengraving to open contacts.
Another solid state device involving dual-side processing is disclosed in U.S. Pat. No. 4,782,028 to Farrier et al. This time, a detector device is processed by first depositing a P.sup.- -type blocking layer and growing an oxide layer on both sides of a substrate before coating an etch resistant layer of Si-nitride. A window is opened through the etch resist and oxide layers by photolithography and the substrate is etched through the window to produce a thinned region on one side. Selective etching of the thinned side and formation of contacts on the non-thinned side is followed by separation of the thinned region of the substrate from its thicker counterpart. Electrical attachment of the contacts to a readout device enables the device as an IR detector.
Both Farrier and van Tangerloo involve multiple dual-side processing steps to produce a solid state device. Neither of these references, however, contemplates dual-side processing to produce an IC.
Re-slicing of a wafer that has been previously cut from a solid ingot to standard thickness has been performed in limited circumstances. In U.S. Pat. No. 4,261,781 to Edmonds et al., a method of re-slicing a wafer, wherein a layer of supporting material is first bound to each side of the wafer, is disclosed. The method requires intimate contact between bonding material and both substrate surfaces. The re-slicing technique of Edmonds can therefore not be performed on a wafer containing a previously processed IC on one or both sides.
U.S. Pat. No. 5,142,256 to Ibaraki uses a vacuum chucking mechanism for holding a wafer vertical prior to re-slicing. The disclosure is drawn primarily to an apparatus for loading an original intact wafer and unloading the two wafers remaining after re-slicing the original wafer. The point of Ibaraki is to speed the re-slicing process.
Both U.S. Pat. No. 5,240,882 to Satoh et al. and Japanese Patent No. Sho 64-19729 disclose further re-slicing techniques. Each of these techniques involves dividing a wafer into two sheets for making discreet components, such as transistors, diodes, and the like.
The re-slicing techniques of Satoh and Jap. Pat. No. Sho 64-19729 are drawn to creating substrates for further processing of discreet electronic components. IC processing is not contemplated, either before or after re-slicing. Moreover, IC processing cannot be performed on substrates prior to re-slicing via the techniques of either Edmonds or Ibaraki because these techniques would undesirably molest the processed IC.